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| LS830 LS831 LS832 LS833 Linear Integrated Systems FEATURES ULTRA LOW DRIFT ULTRA LOW LEAKAGE LOW NOISE LOW CAPACITANCE |VGS1-2 /T|= 5V/C max. IG = 80fA TYP. en= 70nV/Hz TYP. CISS= 3pf MAX. ULTRA LOW LEAKAGE LOW DRIFT MONOLITHIC DUAL N-CHANNEL JFET ABSOLUTE MAXIMUM RATINGS NOTE 1 @ 25C (unless otherwise noted) Maximum Temperatures Storage Temperature Operating Junction Temperature -65 to +150C +150C D1 S1 G2 G1 3 5 S2 Maximum Voltage and Current for Each Transistor NOTE 1 Gate Voltage to Drain or Source 40V -VGSS -VDSO -IG(f) -IG Drain to Source Voltage Gate Forward Current Gate Reverse Current 40V 10mA 10A D1 2 D2 6 D2 1 S1 7 G2 G1 S2 BOTTOM VIEW 22 X 20 MILS Maximum Power Dissipation Device Dissipation @ Free Air - Total 40mW @ +125C LS833 75 25 0.5 0.5 1.0 1.0 UNITS V/C mV pA nA pA nA ELECTRICAL CHARACTERISTICS @ 25C (unless otherwise noted) SYMBOL CHARACTERISTICS LS830 LS831 LS832 5 10 20 |VGS1-2 /T| max. Drift vs. Temperature |VGS1-2| max. -IG max -IG max -IGSS -IGSS Offset Voltage Operating High Temperature At Full Conduction High Temperature 25 0.1 0.1 0.2 0.5 25 0.1 0.1 0.2 0.5 25 0.1 0.1 0.2 0.5 CONDITIONS VDG= 10V VDG= 10V TA= +125C VGS= 0 TA= +125C ID= 30A ID= 30A TA= -55C to +125C VGS= -20V SYMBOL BVGSS BVGGO Yfss Yfs |Yfs1-2/Yfs| IDSS |IDSS1-2/IDSS| VGS(off) or VP VGS IGGO CHARACTERISTICS Breakdown Voltage Gate-to-Gate Breakdown TRANSCONDUCTANCE Full Conduction Typical Operation Mismatch DRAIN CURRENT Full Conduction Mismatch at Full Conduction GATE VOLTAGE Pinchoff Voltage Operating Range GATE CURRENT Gate-to-Gate Leakage MIN. 40 40 70 50 -60 -0.6 --- TYP. 60 -300 100 1 400 2 2 -1 MAX. --500 200 5 1000 5 4.5 4 -- UNITS V V mho mho % A % V V pA CONDITIONS VDS= 0 ID= 1nA IG= 1nA VDG= 10V VDG= 10V ID= 0 VGS= 0 ID= 30A I S= 0 f= 1kHz f= 1kHz VDG= 10V VGS= 0 VDS= 10V VDG= 10V VGG= 20V ID= 1nA ID= 30A Linear Integrated Systems 4042 Clipper Court, Fremont, CA 94538 * TEL: (510) 490-9160 * FAX: (510) 353-0261 SYMBOL YOSS YOS |YOS1-2| CMR CMR NF en CHARACTERISTICS OUTPUT CONDUCTANCE Full Conduction Operating Differential COMMON MODE REJECTION -20 log |VGS1-2/VDS| -20 log |VGS1-2/VDS| NOISE Figure Voltage CAPACITANCE Input Reverse Transfer Drain-to-Drain MIN. -------- TYP. ---90 90 -20 MAX. UNITS 5 0.5 0.1 --1 70 mho mho mho dB dB dB nV/Hz CONDITIONS VDG= 10V VDG= 10V VGS= 0 ID= 30A VDS= 10 to 20V VDS= 5 to 10V VDS= 10V f= 100Hz VDG= 10V NBW= 1Hz VDS= 10V VDS= 10V VDG= 10V ID= 30A ID= 30A VGS= 0 RG= 10M NBW= 6Hz ID= 30A f= 10Hz CISS CRSS CDD ---- ---- 3 1.5 0.1 pF pF pF VGS= 0 VGS= 0 ID= 30A f= 1MHz f= 1MHz TO-71 Six Lead 0.195 DIA. 0.175 0.030 MAX. 0.230 DIA. 0.209 0.150 0.115 TO-78 0.305 0.335 0.335 0.370 MAX. 0.040 0.165 0.185 MIN. 0.500 SEATING PLANE 0.200 0.100 P-DIP 0.320 (8.13) 0.290 (7.37) 0.405 (10.29) MAX. S1 D1 SS G1 1 2 3 4 8 7 6 5 G2 SS D2 S2 0.016 0.019 DIM. A 0.016 0.021 DIM. B 0.029 0.045 2 34 1 5 8 76 6 LEADS 0.019 DIA. 0.016 0.100 0.500 MIN. 0.050 234 1 8 5 6 7 SOIC 0.150 (3.81) 0.158 (4.01) 0.100 45 0.046 0.036 45 0.048 0.028 0.028 0.034 0.188 (4.78) 0.197 (5.00) S1 D1 SS G1 1 2 3 4 8 7 6 5 G2 SS D2 S2 0.228 (5.79) 0.244 (6.20) NOTES: 1. These ratings are limiting values above which the serviceability of any semiconductor may be impaired. Linear Integrated Systems 4042 Clipper Court, Fremont, CA 94538 * TEL: (510) 490-9160 * FAX: (510) 353-0261 |
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